5238-DS03-405-R datasheet(64/76 Pages) BOARDCOM

64 / 76 page

BCM5238

Advance Data Sheet

1/31/03

Broa d c om Co rp o r a t i o n

Page 56

Timing and AC Characteristics

Document

5238-DS03-405-R

Se ction 7: Timing an d AC Char acte r istics

All digital output timing is specified at CL = 30 pF.

Output rise/fall times are measured between 10% and 90% of the output signal swing. Input rise/fall times are measured

between VIL maximum and VIH minimum. Output signal transitions are referenced to the midpoint of the output signal swing.

Input signal transitions are referenced to the midpoint between VIL maximum and VIH minimum.

Figure 4: Clock and Reset Timing

When in S3MII mode, SSMII-TXC, the SMII source synchronous transmit clock must be running before RESET rising edge.

Also, SSMII-TXC must be frequency-locked to REF_CLK.

Table 53: Clock Timing

Parameter

Symbol

Minimum

Typical

Maximum

Units

REF_CLK Cycle time (125-MHz operation)

CK_CYCLE

nanoseconds

REF_CLK High/Low time (125-MHz operation)

CK_HI

CK_LO

nanoseconds

REF_CLK Rise/Fall time (125-MHz operation)

CK_EDGE

–

nanoseconds

Table 54: Reset Timing

Parameter

Symbol

Minimum

Typical

Maximum

Units

Reset pulse length with stable REF_CLK input

RESET_LEN

–

µs

Activity after end of reset

RESET_WAIT

100

–

µs

Reset rise/fall time

RESET_EDGE

–

REF_CLK

RESET

Normal PHY

begin here

RESET_LEN

RESET_WAIT

CK_HI

CK_CYCLE

CK_EDGE

CK_LO

CK_EDGE

activity can

RESET_EDGE

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