S70FS01GS datasheet(22/141 Pages) CYPRESS

22 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 22 of 141

3.4

Configuration Register Effects on the Interface

The configuration register 2 volatile bits 3 to 0 (CR2V[3:0]) select the variable latency for all array read commands except Read and

Read SDFP (RSFDP). Read always has zero latency cycles. RSFDP always has 8 latency cycles. The variable latency is also used

in the OTPR, and RDAR commands.

The configuration register bit1 (CR1V[1]) selects whether Quad mode is enabled to switch WP# to IO2 function, RESET# to IO3

function, and thus allow Quad I/O Read and QPI mode commands. Quad mode must also be selected to allow DDR Quad I/O Read

commands.

3.5

Data Protection

Some basic protection against unintended changes to stored data are provided and controlled purely by the hardware design. These

are described below. Other software managed protection methods are discussed in the software section of this document.

3.5.1

Power-Up

When the core supply voltage is at or below the VDD (Low) voltage, the device is considered to be powered off. The device does not

react to external signals, and is prevented from performing any program or erase operation. Program and erase operations continue

to be prevented during the Power-on Reset (POR) because no command is accepted until the exit from POR to the Interface

Standby state.

3.5.2

Low Power

When VDD is less than VDD (Cut-off) the memory device will ignore commands to ensure that program and erase operations can not

start when the core supply voltage is out of the operating range.

3.5.3

Clock Pulse Count

The device verifies that all non-volatile memory and register data modifying commands consist of a clock pulse count that is a

multiple of eight bit transfers (byte boundary) before executing them. A command not ending on an 8 bit (byte) boundary is ignored

and no error status is set for the command.

3.5.4

Deep Power Down (DPD)

In DPD mode the device responds only to the Release from DPD command (RES ABh). All other commands are ignored during

DPD mode, thereby protecting the memory from program and erase operations.

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