MB90598GPF datasheet(3/52 Pages) CYPRESS

3 / 52 page

Document Number: 002-07700 Rev. *B

Page 3 of 52

MB90595G Series

1. Product Lineup

Features

MB90598G

MB90F598G

MB90V595G

Classification

Mask ROM product

Flash ROM product

Evaluation product

ROM size

128 Kbytes

Boot block

Hard-wired reset vector

None

RAM size

4 Kbytes

6 Kbytes

Emulator-specific power supply



None

CPU functions

The number of instructions: 351

Instruction bit length: 8 bits, 16 bits

Instruction length: 1 byte to 7 bytes

Data bit length: 1 bit, 8 bits, 16 bits

Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz)

Interrupt processing time: 1.5

s

(at machine clock frequency of 16 MHz, minimum value)

UART0

Clock synchronized transmission (500 K/1 M/2 Mbps)

Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500

/500000 bps at machine clock frequency of 16 MHz)

Transmission can be performed by bi-directional serial transmission or by master/slave connection.

UART1(SCI)

Clock synchronized transmission (62.5 K/125 K/250 K/500 K/1 Mbps)

Clock asynchronized transmission (1202/2404/4808/9615/31250 bps)

Transmission can be performed by bi-directional serial transmission or by master/slave connection.

8/10-bit A/D converter

Conversion precision: 8/10-bit can be selectively used.

Number of inputs: 8

One-shot conversion mode (converts selected channel once only)

Scan conversion mode (converts two or more successive channels and can program

up to 8 channels)

Continuous conversion mode (converts selected channel continuously)

Stop conversion mode (converts selected channel and stop operation repeatedly)

8/16-bit PPG timers

(6 channels)

Number of channels: 6 (8/16-bit

 6 channels)

PPG operation of 8-bit or 16-bit

A pulse wave of given intervals and given duty ratios can be output.

Pulse interval: fsys, fsys/21, fsys/22, fsys/23, fsys/24 (fsys

 system clock frequency)

128

s (fosc = 4MHz: oscillation clock frequency)

16-bit Reload timer

Number of channels: 2

Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)

Supports External Event Count function

16-bit

I/O tim-

16-bit

Output compares

Number of channels: 4

Pin input factor: A match signal of compare register

Input captures

Number of channels: 4

Rewriting a register value upon a pin input (rising, falling, or both edges)

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