ADC14155

100 pF

x 3

100 pF

D7

D6

D5

D4

D11

D10

D9

D8

D3

D2

D1

(LSB) D0

48

0.1 PF

x 6

+3.3V from

Regulator

49.9

47

45

42

Flux XFMR: ADT1-1WT or ETC1-1T

Balun XFMR: ADT1-12 or ETC1-1-13

0.1 PF

12.1

12.1

0.1 PF

1

CLK_SEL/DF

CLK+

CLK_SEL/DF

PD

PD

15 pF

0.1 PF

0.1 PF

10 PF

0.1 PF

D12

(MSB) D13

17

18

19

20

21

22

23

24

27

28

29

30

31

32

0.1 PF

x 3

4

5

7

8

11

LC4032V-25TN48C

PLD

Output

Word

0.1 PF

34

33

OVR

DRDY

22

0.1 PF

10 PF

10 PF

24.9

24.9

100 pF

x 6

+3.3V from

Regulator

+1.8V from

Regulator

24.9

0.1 PF

1

CLK-

12

0.1 PF

NC7WV125K8X

High Speed Buffer

100 pF

x 4

0.1 PF

x 4

+1.8V from

Regulator

100 pF

x 2

0.1 PF

x 2

+3.3V from

Regulator

1k

1k

0.1 PF

44

46

43

VRN

VRM

V RP

V RP

VRN

VRM

24

ADC14155QML-SP

SNAS378J – NOVEMBER 2008 – REVISED MARCH 2018

www.ti.com

Product Folder Links: ADC14155QML-SP

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Copyright © 2008–2018, Texas Instruments Incorporated

(1)

Pre and post irradiation limits are identical to those listed in the Electrical Characteristics tables. Radiation testing is performed per MIL-

STD-883, Test Method 1019.

8.2 Typical Application

Figure 23. Application Circuit Using Transformer Drive Circuit

8.2.1 Design Requirements

We recommend that the following conditions be observed for operation of the ADC14155:

3 V

5 MHz

1-V internal reference

0.9 V

8.2.2 Detailed Design Procedure

Digital outputs consist of the 1.8 V CMOS signals D0-D13, DRDY and OVR.

The ADC14155 has 16 CMOS compatible data output pins: 14 data output bits corresponding to the converted

input value, a data ready (DRDY) signal that should be used to capture the output data and an over-range

indicator (OVR) which is set high when the sample amplitude exceeds the 14-bit conversion range. Valid data is

present at these outputs while the PD pin is low.

Data should be captured and latched with the rising edge of the DRDY signal. Depending on the setup and hold

time requirements of the receiving circuit (ASIC), either the rising edge or the falling edge of the DRDY signal

can be used to latch the data. Generally, rising-edge capture would maximize setup time with minimal hold time;

while falling-edge-capture would maximize hold time with minimal setup time. However, actual timing for the

falling-edge case depends greatly on the CLK frequency and both cases also depend on the delays inside the

ASIC. Refer to the ADC14155 Converter Electrical Characteristics (Continued) Timing and AC Characteristics(1)

table.