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S25FL032P bảng dữ liệu(PDF) 13 Page - Cypress Semiconductor

tên linh kiện S25FL032P
Giải thích chi tiết về linh kiện  32-Mbit 3.0 V Flash Memory
PDF  60 Pages
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nhà sản xuất  CYPRESS [Cypress Semiconductor]
Trang chủ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S25FL032P bảng dữ liệu(HTML) 13 Page - Cypress Semiconductor

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Document Number: 002-00650 Rev. *L
Page 13 of 60
S25FL032P
Note
(Default) indicates the value of each Configuration Register bit set upon initial factory shipment.
7.9
Data Protection Modes
Cypress SPI Flash memory devices provide the following data protection methods:
 The Write Enable (WREN) command: Must be written prior to any command that modifies data. The WREN command sets the
Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up or after the device completes the following
commands:
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Register (WRR)
– Parameter 4 KB Sector Erase (P4E)
– Parameter 8 KB Sector Erase (P8E)
– Quad Page Programming (QPP)
– OTP Byte Programming (OTPP)
 Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be
read but not programmed or erased. Table 6 and Table 7 shows the sizes and address ranges of protected areas that are defined
by Status Register bits BP2:BP0.
 Hardware Protected Mode (HPM): The Write Protect (W#/ACC) input and the Status Register Write Disable (SRWD) bit together
provide write protection.
 Clock Pulse Count: The device verifies that all program, erase, and Write Register commands consist of a clock pulse count that
is a multiple of eight before executing them.
Table 5. Configuration Register Table
Bit
Bit Name
Bit Function
Description
7NA
Not Used
6NA
Not Used
5TBPROT
Configures start of block protection
1 = Bottom Array (low address)
0 = Top Array (high address) (Default)
4NA
Do not use
3
BPNV
Configures BP2-0 bits in the Status Register
1 = Volatile
0 = Nonvolatile (Default)
2TBPARM
Configures Parameter sector location
1 = Top Array (high address)
0 = Bottom Array (low address) (Default)
1QUAD
Puts the device into Quad I/O mode
1 = Quad I/O
0 = Dual or Serial I/O (Default)
0
FREEZE
Locks BP2-0 bits in the Status Register
1 = Enabled
0 = Disabled (Default)



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