PIC16F767 datasheet(57/276 Pages) MICROCHIP

57 / 276 page

 2004 Microchip Technology Inc.

DS30498C-page 55

PIC16F7X7

TABLE 5-1:

PORTA FUNCTIONS

TABLE 5-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name

Bit#

Buffer

Function

RA0/AN0

bit 0

TTL

Input/output or analog input.

RA1/AN1

bit 1

TTL

Input/output or analog input.

RA2/AN2/VREF-/CVREF

bit 2

TTL

Input/output or analog input or VREF-.

RA3/AN3/VREF+

bit 3

TTL

Input/output or analog input or VREF+.

RA4/T0CKI/C1OUT

bit 4

Input/output or external clock input for Timer0. Output is

open-drain type.

RA5/AN4/LVDIN/SS/C2OUT

bit 5

TTL

Input/output or slave select input for synchronous serial port or

analog input.

OSC2/CLKO/RA6

bit 6

Input/output, connects to crystal or resonator, oscillator output or

1/4 the frequency of OSC1 and denotes the instruction cycle in

RC mode.

OSC1/CLKI/RA7

bit 7

ST/CMOS(1) Input/output, connects to crystal or resonator or oscillator input.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1:

This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

05h

PORTA

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0

xx0x 0000

uu0u 0000

85h

TRISA

PORTA Data Direction Register

1111 1111

9Fh

ADCON1

ADFM

ADCS2

VCFG1 VCFG0 PCFG3

PCFG2

PCFG1

PCFG0

0000 0000

9Ch

CMCON

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

0000 0111

9Dh

CVRCON

CVREN CVROE

CVRR

—

CVR3

CVR2

CVR1

CVR0

000- 0000

Legend:

= unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Note:

When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of

the following modes, where PCFG2:PCFG0 = 100, 101, 11x.

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