HT85F2250 datasheet(77/187 Pages) HOLTEK

77 / 187 page

Rev. 1.10

77 of 187

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A/D Flash 8051 Core Low Pin Count MCU

HT85F2250/HT85F2262

Watchdog Reset

All devices contain a Watchdog Timer which is used as a protection feature. The Watchdog

Timer has to be periodically cleared by the application program and prevented from overflowing

during normal MCU operation. However should the program enter an endless loop or should

external environmental conditions such as noise causes the device to jump to unpredicted program

locations, the Watchdog Timer will overflow and generate an MCU reset. Refer to the Watchdog

Timer section for more details regarding the Watchdog Timer operation.

When a Watchdog Reset occurs the WDTS bit in the IP0 register will be set to indicate the reset

source. Note that this bit must be reset by the application program.

IP0 Register

SFR Address: B8h

Bit

Name

—

WDTS

PT�

PS0

PT1

PX1

PT0

PX0

R/W

—

R/W

POR

—

Bit 7

Unimplemented, read as “0”

Bit 6

WDTS: Watchdog timer reset indication flag

0: No Watchdog timer reset

1: Watchdog timer reset

This bit must be cleared by the application program as it will not be automatically

cleared by hardware.

Bit 5

PT2: Timer 2 Interrupt priority

Described elsewhere

Bit 4

PS0: Serial Port 0 Interrupt priority

Described elsewhere

Bit 3

PT1: Timer 1 Interrupt priority

Described elsewhere

Bit 2

PX1: External interrupt 1 priority

Described elsewhere

Bit 1

PT0: Timer 0 Interrupt priority

Described elsewhere

Bit 0

PX0: External interrupt 0 priority

Described elsewhere

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