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AD7293 bảng dữ liệu(PDF) 30 Page - Analog Devices

tên linh kiện AD7293
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AD7293 bảng dữ liệu(HTML) 30 Page - Analog Devices

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AD7293
Data Sheet
Rev. B | Page 30 of 78
AVDD AND AVSS ALARM
There are comparators on AVDD (+3.6 V typical) and AVSS
(−4.1 V typical) that can be routed to the ALERTx pins or can
be used to control the PA_ON state and to put the bipolar
DACs/integrator outputs in the clamp state. By default, these
alarms are enabled.
When AVSS is greater than −4.1 V, there is a mask register
available whereby an alert of AVSS or AVDD is not creating an
alert on the ALERTx pin.
MAXIMUM AND MINIMUM PAGES
The maximum and minimum pages contain storage registers
for the maximum and minimum conversion results. This
function is useful when monitoring the minimum and maxi-
mum conversion values over time is required.
HYSTERESIS
The hysteresis value determines the reset point for the ALERTx
pin and/or software alert bit if a violation of the limits occurs. The
hysteresis register stores the hysteresis value when using the
limit registers. Each pair of limit registers has a dedicated hysteresis
register (see Figure 50). If software is periodically polling the
device to detect an alert, the hysteresis can be useful to ensure
that no out of limit condition is missed.
Figure 50. Hysteresis
HIGH LIMIT
LOW LIMIT
HIGH LIMIT – HYSTERESIS
LOW LIMIT + HYSTERESIS
TIME
INPUT SIGNAL
ALERT SIGNAL



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