CS53L32A datasheet(28/40 Pages) CIRRUS

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CS53L32A

DS513F1

Address Bit

AD0/CS (Control Port Mode)

(

Input) - In Two Wire mode, AD0 is a chip

address bit. CS is used to enable the control port interface in SPI mode.

MCLK Divide Enable

DIV (Stand-Alone Mode)

(

Input) - When high, the chip will enter High Rate

Mode. When this pin is low, the chip will enter Base Rate Mode.

Serial Control Data I/O

SDA/CDIN (Control Port Mode)

(

Input/Output) - In Two Wire mode, SDA is

a data I/O line. CDIN is the input data line for the control port interface in SPI

mode.

Digital Interface Format

DIF (Stand-Alone Mode)

(

Input) - The required relationship between the

Left/Right clock, serial clock and serial data is defined by the Digital Interface

Format.

Serial Control

Interface Clock

SCL/CCLK (Control Port Mode)

(

Input) - Clocks the serial control data into

or from SDA/CDIN/DIF.

Channel Select

ChSEL (Stand-Alone Mode)

(

Input) - The analog data path is determined

by the Channel Select bit. These options are detailed in Table 18.

Anti-Aliasing Capacitors

11, 12

AFLTR, AFLTL

(

Output) - Anti-aliasing capacitors for the left and right chan-

nels. An external capacitor is required from AFLTR and AFLTL to ground, as

shown in Figure 5. AFLTR and AFLTL are not intended to supply external

current, and any current drawn from these pins will alter device perfor-

mance.

Positive Voltage

Reference

FILT+

(

Output) - Positive reference for internal sampling circuits. An external

capacitor is required from FILT+ to ground, as shown in Figure 6. The rec-

ommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of

PSRR at 60 Hz. FILT+ is not intended to supply external current. FILT+ has

a typical source impedance of 250 k

Ω and any current drawn from this pin

will alter device performance.

Analog Inputs

14, 15, 17, and 18

AIN_R1, AIN_L1, AIN_R2, AIN_L2

(

Input) - Channel 1/Channel 2 analog

inputs.

Sample

Rate

(kHz)

MCLK (MHz)

HRM

BRM

128x

192x

256x*

384x*

256x

384x

512x

768x*

1024x*

4.0960

6.1440

8.1920

12.2880

8.1920

12.2880

16.3840

24.5760

32.7680

44.1

5.6448

8.4672

11.2896

16.9344

11.2896

16.9344

22.5792

32.7680

45.1584

6.1440

9.2160

12.2880

18.4320

12.2880

18.4320

24.5760

36.8640

49.1520

8.1920

12.2880

16.3840

24.5760

88.2

11.2896

16.9344

22.5792

33.8688

12.2880

18.4320

24.5760

36.8640

* MCLKDIV = 1 in Control Port mode or DIV= Hi when in Stand-Alone mode

Table 16. Common Clock Frequencies

DIF

DESCRIPTION

I2S, up to 24-bit data

Left Justified, up to 24-bit data

Table 17. Digital Interface Format - DIF (Stand-Alone Mode)

ChSEL

DESCRIPTION

Channel 1 directly to A/D

Channel 2 with 32dB of gain

Table 18. Channel Select Options

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