FDMF2011 datasheet(26/31 Pages) ONSEMI

26 / 31 page

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FDMF2011 Rev.1.0

•

Switching losses - Rising and falling time

parasitic

inductance

can

measured in the application, listed below

assumed zero inductance.

Switching OFF loss

Switching ON loss

•

Gate drive loss

•

Quiescent current power loss – Current

is still drawn from the VDD and HB pins

for internal and level shifting circuitry

without load (RG=Open). Power loss by

quiescent current is

•

Supply current power loss(RG=0Ω) is

•

Total power loss in the FDMF2011 is

equal to the power dissipation caused by

gate driver and Power MOSFETs,

Once the designer estimates power dissipation

in the gate driver and MOSFETs, junction

temperature can be calculated using thermal

resistance (ΘJA) and ambient temperature as

followings and also can calculate maximum

allowable motor current:

Continuous current flowing out of

SW node

Continuous current flowing out of the module

SW node is typical of a heavily loaded switched-

mode power stage that is operating in a

synchronous buck converter topology. In this

mode, the power stage is supplying current from

VIN into an inductive load. Figure 66 shows and

example

synchronous

buck

convert

operating in CCM with positive inductor current.

Figure 66. Synchronous Buck Operating

in CCM with positive inductor current

During this operating mode, the HS MOSFET

(Q1)

will undergo

hard-switched

inductive

turn-on and turn-off events, while LS MOSFET

(Q2) will undergo soft switching and body

diode recovery. Hard-switching often results in

large switching spikes on Q1 and Q2 VDS as

well as PH to VSS and BOOT to VSS pins.

Peak switching spikes are often positively

correlated to load current.

Continuous current flowing into

SW node.

Continuous current flowing into the module

SW node is typical of a heavily loaded

switched-mode power stage that is operating

in a synchronous boost converter topology.

Continuous inductor current flowing in to the

module SW node is typical operation of a

synchronous boost converter, as shown in

Figure 67.

)

/(R

;

)/i

where

)

(

DRV_OFF

PLATEAU

G(OFF)

GS2

OFF

DS(OFF)

SW(OFF)

⋅

Charge

Output

Qoss

)

/(R

;

)/i

where

)

Qoss

(

DRV_ON

PLATEAU

G(ON)

GS2

DS(ON)

SW(ON)

⋅

DRV

GATE

⋅

HBO

DDO

supply

⋅

HBQ

DDQ

Quiescent

⋅

supply

Gate

Cond

total

)

(

total

⋅

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