▪ Two low skew, low additive jitter LVDS output pairs
▪ One differential clock input pair
▪ Differential CLK, nCLK pairs can accept the following
differential input levels: LVDS, CML
▪ Maximum input clock frequency: 51.2GHz
▪ Output skew: 3ps (typical)
▪ Propagation delay: 400ps (maximum)
▪ Low additive phase jitter, RMS; fREF = 156.25MHz,
10kHz–20MHz: 34fs (typical)
▪ Device current consumption (IDD):
• 40mA typical: 1.8V
• 50mA typical: 2.5V
▪ Full 1.8V or 2.5V supply voltage
▪ Lead-free (RoHS 6), 16-Lead VFQFN package
▪ -40°C to 85°C ambient operating temperature
▪ Supports case temperature up to +105°C
▪ Supports PCI Express Gen 1-5