1. General description
The 74AXP4T245 is an 4-bit dual supply translating transceiver with 3-state outputs that enable
bidirectional level translation. The device can be used as two 2-bit transceivers or as a 4-bit
transceiver. It features four 2-bit input-output ports (nAn and nBn), a direction control input (nDIR),
a output enable input (nOE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can
be supplied at any voltage between 0.9 V and 5.5 V making the device suitable for translating
between any of the low voltage nodes (0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). No power
supply sequencing is required and output glitches during power supply transitions are prevented
using patented circuitry. As a result glitches will not appear on the outputs for supply transitions
during power-up/down between 20 mV/μs and 5.5 V/s.
Pins nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B). A HIGH
on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to
nAn. The output enable input (nOE) can be used to disable the outputs so the buses are effectively
isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing any damaging backflow current through the device when it is
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both nAn and nBn
are in the high-impedance OFF-state.
2. Features and benefits
• Wide supply voltage range:
• VCC(A): 0.9 V to 5.5 V
• VCC(B): 0.9 V to 5.5 V
• Low input capacitance; CI = 1.2 pF (typical)
• Low output capacitance; CO = 3.6 pF (typical)
• Low dynamic power consumption; CPD = 10 pF (typical)
• Low static power consumption; ICC = 2 μA (25 °C maximum)
• High noise immunity
• Complies with JEDEC standard:
• JESD8-12 (1.1 V to 1.3 V; inputs)
• JESD8-11 (1.4 V to 1.6 V)
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD12-6 (4.5 V to 5.5 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2 kV
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1 kV
• Latch-up performance exceeds 100 mA per JESD78D Class II
• Inputs accept voltages up to 5.5 V
• Low noise overshoot and undershoot < 10% of VCCO
• IOFF circuitry provides partial power-down mode operation
• Specified from -40 °C to +125 °C