SA4301ASAR datasheet(13/23 Pages) SAMES

13 / 23 page

SPEC-1538 (REV. 7)

13/23

29-09-2017

SA4301A

In STANDARD mode the nominal LED output frequency is

��_�� =

��_��

…(4)

where

fLED_FAST is the FAST mode output frequency as per Equation

3 and

DF_LED is the LED divider selected by RA, RB and FMS

according to Table 2.

The timing values given below are based on the nominal

frequency value of the internal oscillator.

tL = 1/fLED_FAST in FAST mode (fLED_FAST as per Equation 3)

= 1/fLED_STD in STANDARD mode (fLED_STD as per

Equation 4)

tLP = 91.5ms when tL > 183ms in STANDARD mode

= tL/2 when tL < 183ms in STANDARD mode

= 70μs in FAST mode

Figure 9: LED pulse output waveform

Motor Pulse Output (MON, MOP)

The MON and MOP pins are complimentary outputs with a

frequency

proportional

the

average

active

power

consumption measured. These active high outputs can be

used to either directly drive a stepper motor counter or an

electro-mechanical impulse counter. The Rated Condition

Select inputs (RA, RB) as well as the Fast Mode Select input

(FMS) allow the selection of different output frequencies

corresponding to different meter constants. Figure 10

indicates the timing of these signals.

The nominal output frequency of each motor output is given

by:

�� =

��_��

where

…(5)

fLED_STD is the output frequency of the LED output in

STANDARD mode as per Equation 4 and

DF_MO is the motor divider selected by RA, RB and FMS

according to Table 2.

When connecting a stepper motor counter between MON and

MOP the output pulse rate is effectively doubled because the

pulses on both MON and MOP contribute to incrementing the

counter.

The timing values given below are based on the nominal

frequency value of the internal oscillator.

= 1/fMOT (fMOT as per Equation 5)

tMP

= 220ms when tM > 440ms

= tM/2 when tM < 440ms

tMS

= tM/2

tMSP = tMS-tMP when tM > 440ms

= 7.8μs when tM < 440ms

Figure 10: Motor pulse output waveform

Phase Direction Output (PH/DIR)

The PH/DIR output enables either direction or missing phase

information on the multiplexed LED driver outputs (PH1, PH2

and PH3). This output pin switches between logic 0 and logic

1 at a frequency of approximately 110Hz. A logic 0 enables

energy direction information and a logic 1 enables missing

phase information on the LED driver outputs. The PH/DIR

output is used in conjunction with the individual LED driver

outputs to display information concerning each individual

channel as illustrated in Figure 11. It is also used in

conjunction with the RA, RB and MS inputs to set up the

SA4301A.

LED Drivers (PH1, PH2, PH3)

When used in conjunction with the PH/DIR signal the LED

driver outputs will indicate individual channel energy direction

and individual channel missing phase conditions as follows:

PH/DIR = 1 (Voltage fail / phase sequence error): When

PH/DIR is high (logic 1) the individual channel voltage

information is available on the PH1, PH2 and PH3 pins. A

logic 1 on any of these pins indicates the corresponding

channels voltage is missing. This is based on the SA4301A

not detecting a sufficiently large input current amplitude

(approximately 1µARMS) on the specific voltage sense input.

The outputs will be set to logic 0 when the input current on

the corresponding channel is larger than approximately

1µARMS thereby indicating that the corresponding phase

voltage is present. Referring to Figure 11, the voltage LED for

a specific channel will be activated when the phase voltage is

present and de-activated when the phase voltage is missing.

A power-on reset at start-up will set the voltage fail indication

for all channels to high (logic 1). Each missing phase LED will

therefore be de-activated until a valid phase voltage is

detected. In the case of a phase sequence error all three

MSP

MON

MOP

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