M52036SP

Rev.1.0, Sep.22.2003, page 11 of 13

5) VERT S/S ADJ (pins [10])

The threshold voltage is approximately 1 V when no external adjustment is provided. The threshold voltage is

dependent on IC internal resistance. Pin [10] may be open; however, if noise may give adverse effect, ground the

pin with capacitor.

When the H element cannot be lowered sufficiently, connect resistance between pin [10] and Vcc to change the

When there are serration pulses or other pulses during the V period, provide resistance such that the threshold

2. CP-Width

Timing terminal (pins [20])

The time constant depends on the current flowing out through pin [20] and the capacitance of the timing terminal.

The current flowing out through pin [20] is usually determined by the terminal voltage and the resistance of

externally attached resistor. A pulse width of 0.7

µ sec is obtained by an 18 kΩ (or 200 µA) resistor and a 100 pF

capacitor both installed externally.

3. Output stage

1) Logic output (pins [1], [2], [18] and [19])

This output system is illustrated in the figure shown below. The internal load resistance of this IC is 20 k

Ω.

2) Pulse output (pins [13], [14], [15] and [17])

This output system is of open collector type as illustrated in the figure shown below. Approximately 6 mA can be

charged in.

3) Power supply

Supply 12 V to pin [16].

For the pulse output power, supply a digital Vcc of 5 to 12 V as illustrated below.