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AD7452BRTZ-R2 bảng dữ liệu(PDF) 10 Page - Analog Devices

tên linh kiện AD7452BRTZ-R2
Giải thích chi tiết về linh kiện  Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23
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AD7452BRTZ-R2 bảng dữ liệu(HTML) 10 Page - Analog Devices

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Data Sheet
AD7452
Rev. C | Page 9 of 24
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+ – VIN– (that is, –VREF + 1 LSB),
after the zero code error has been adjusted out.
Track-and-Hold Acquisition Time
The minimum time required for the track-and-hold amplifier
to remain in track mode for its output to reach and settle to
within 0.5 LSB of the applied input signal.
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale fre-
quency, f, to the power of a 100 mV p-p sine wave applied to the
ADC VDD supply of frequency fS. The frequency of this input
varies from 1 kHz to 1 MHz.
PSRR(dB) = 10log(Pf/PfS)
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency fS in the ADC output.



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