HCF4013B

4/9

(1) Input tr, tf = 5ns

(2) If more than unit is cascaded in a parallel clocked application, tr should be made less than or equal to the sum of the fixed propagation

delay time at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.

Symbol

Parameter

Test Condition

Value (*)

Unit

Min.

Typ.

Max.

(CLOCK to Q or Q outputs)

5

150

300

ns

10

65

130

15

45

90

Propagation Delay Time

(SET to Q or RESET to Q)

5

150

300

ns

10

65

130

15

45

90

Propagation Delay

Time(SET to Q or RESET

to Q)

5

200

400

ns

10

85

170

15

60

120

5

100

200

ns

10

50

100

15

40

80

(1)

Maximum Clock Input

Frequency

5

3.5

7

MHz

10

8

16

15

12

24

Clock Pulse Width

5

140

70

ns

10

60

30

15

40

20

(2)

Clock Input Rise or Fall

Time

515

µs

10

4

15

1

Set or Reset Pulse Width

5

180

90

ns

10

80

40

15

50

25

Data Setup Time

5

40

20

ns

10

20

10

15

15

7