REV. B

–13–

AD8380

In order to obtain the best matching, the traces to each of the

VREFHI pins of the AD8380s should be connected by an

approximately same length and same width circuit trace in a

“star” configuration. The source of the VREFHI voltage should

be at the center of the “star.” Therefore, the VREFHI currents

for two devices will not share a significant length of circuit trace,

and each trace will provide an approximately equal voltage drop.

In addition, if the VREFHI traces must be long, then the traces

should be widened to minimize differences in the voltage drops

due to differences in the VREFHI input currents of different

AD8380s. The dc resistance of these traces should be less than

100 m

Ω. If the VREFHI input current is about 1 mA, then the

voltage drop will be about 100

µV.

For example, if a trace length is 5 in. long (13 cm.), then the

trace width for a 1 oz. copper foil should be wider than 0.025 in.

(0.7 mm) in order to keep the trace impedance below 100 m

Ω.

Driving a Capacitive Load

A purely capacitive load can react with output impedance of the

AD8380 resulting in overshoot and ringing in its step response.

To minimize this effect, and optimize settling time, it is recom-

mended that a 25

Ω resistor be placed in series with each of the

driver’s outputs as shown in Figure 10.

2.500V

3.3V

10V

15V

CLK

10

DB[0:9]

XFR

E/

O

R/

L

STSQ/CS

3

A[0:2]

INV

STBY

0.1 F

DVCC

VREFHI

VREFLO

AVCCDAC

AVCCBIAS

AVCC0,1

AVCC2,3

AVCC4,5

VMID

DVEE

AVEEDAC

BYP

AVEEBIAS

AVEE0

AVEE1,2

AVEE3,4

AVEE5

LOGIC

DAC

BIAS

DRIVERS

6

VID0 – VID5

7V

10 F

0.1 F

0.1 F

0.1 F

0.1 F

0.1 F

22 F

10 F

0.1 F

24.9

(TYP FOR 6)

10 F

22 F

10 F

0.1 F

0.1 F

0.1 F

Figure 10. Interface Drawing