AD5662ARM datasheet(5/20 Pages) AD

tên linh kiện	AD5662ARM

Giải thích chi tiết về linh kiện	2.7 V to 5.5 V, 250 uA, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23

PDF	20 Pages

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Preliminary Technical Data

AD5662

Rev. PrA | Page 5 of 20

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.

Limit at TMIN, TMAX

Parameter

VDD = 2.7 V to 3.6 V

VDD = 3.6 V to 5.5 V

Unit

Conditions/Comments

t11

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC to SCLK falling edge setup time

ns min

Data setup time

4.5

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

ns min

Minimum SYNC high time

ns min

SYNC rising edge to sclk fall ignore

t10

ns min

SCLK falling edge to SYNC fall ignore

1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V.

DIN

SYNC

SCLK

DB23

DB0

t10

Figure 2. Serial Write Operation

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