M95256, M95128

18/39

Write to Memory Array (WRITE)

As shown in Figure 13., to send this instruction to

the device, Chip Select (S) is first driven Low. The

bits of the instruction byte, address byte, and at

least one data byte are then shifted in, on Serial

Data Input (D).

The instruction is terminated by driving Chip Se-

lect (S) High at a byte boundary of the input data.

In the case of Figure 13., this occurs after the

eighth bit of the data byte has been latched in, in-

dicating that the instruction is being used to write

a single byte. The self-timed Write cycle starts,

ble 18. to Table 22.), at the end of which the Write

in Progress (WIP) bit is reset to 0.

If, though, Chip Select (S) continues to be driven

Low, as shown in Figure 14., the next byte of input

data is shifted in, so that more than a single byte,

starting from the given address towards the end of

the same page, can be written in a single internal

Write cycle.

Each time a new data byte is shifted in, the least

significant bits of the internal address counter are

incremented. If the number of data bytes sent to

the device exceeds the page boundary, the inter-

nal address counter rolls over to the beginning of

the page, and the previous data there are overwrit-

ten with the incoming data. (The page size of

these devices is 64 bytes).

The instruction is not accepted, and is not execut-

ed, under the following conditions:

–

if the Write Enable Latch (WEL) bit has not

been set to 1 (by executing a Write Enable

instruction just before)

–

if a Write cycle is already in progress

–

if the device has not been deselected, by Chip

Select (S) being driven High, at a byte

boundary (after the eighth bit, b0, of the last

data byte that has been latched in)

–

if the addressed page is in the region

protected by the Block Protect (BP1 and BP0)

bits.

Figure 13. Byte Write (WRITE) Sequence

Note: The most significant address bits (b15 for the M95256, and bits b15 and b14 for the M95128) are Don’t Care.

C

D

AI01795D

S

Q

15

2

1

3456789 10

20 21 22 23 24 25 26 27

14 13

3210

28 29 30

High Impedance

Instruction

16-Bit Address

0

765432

0

1

Data Byte

31