AR0130CSSC00SPBA0-DP1 datasheet(3/39 Pages) ONSEMI

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AR0130CS

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Figure 1. Block Diagram

Control Registers

Analog Processing and

A/D Conversion

Active Pixel Sensor

(APS)

Array

Pixel Data Path

(Signal Processing)

Timing and Control

(Sequencer)

Auto Exposure

and Stats Engine

OTPM

Memory

PLL

External

Clock

Parallel

Output

Trigger

Two-wire

Serial

Interface

Power

User interaction with the sensor is through the two−wire

serial bus, which communicates with the array control,

analog signal chain, and digital signal chain. The core of the

sensor is a 1.2 Mp Active− Pixel Sensor array. The timing

and control circuitry sequences through the rows of the

array, resetting and then reading each row in turn. In the time

interval between resetting a row and reading that row, the

pixels in the row integrate incident light. The exposure is

controlled by varying the time interval between reset and

readout. Once a row has been read, the data from the

columns is sequenced through an analog signal chain

(providing offset correction and gain), and then through an

analog−to−digital converter (ADC). The output from the

ADC is a 12−bit value for each pixel in the array. The ADC

output passes through a digital processing signal chain

(which provides further data path corrections and applies

digital gain). The pixel data are output at a rate of up to

74.25 Mp/s, in parallel to frame and line synchronization

signals.

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