WM8976GEFLSLASHRV datasheet(64/83 Pages) WOLFSON

64 / 83 page

WM8976

Preliminary Technical Data

PTD Rev 2.0 February 2005

Figure 37 PLL and Clock Select Circuit

The PLL frequency ratio R = f2/f1 (see Figure 37) can be set using the register bits PLLK and PLLN:

PLLN = int R

PLLK = int (2

24 (R-PLLN))

EXAMPLE:

MCLK=12MHz, required clock = 12.288MHz.

R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a

selectable divide by N after the PLL which should be set to divide by 2 to meet this requirement.

Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.

R = 98.304 / 12 = 8.192

PLLN = int R = 8

k = int ( 2

24 x (8.192 – 8)) = 3221225 = 3126E9h

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLLPRESCALE

Divide MCLK by 2 before input to

PLL

R36

PLL N value

3:0

PLLN

1000

Integer (N) part of PLL input/output

frequency ratio. Use values greater

than 5 and less than 13.

R37

PLL K value

5:0

PLLK [23:18]

0Ch

R38

PLL K Value

8:0

PLLK [17:9]

093h

R39

PLL K Value

8:0

PLLK [8:0]

0E9h

Fractional (K) part of PLL1

input/output frequency ratio (treat as

one 24-digit binary number).

Table 53 PLL Frequency Ratio Control

The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings

are shown in Table 54.

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