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74AC843 bảng dữ liệu(PDF) 2 Page - National Semiconductor (TI) |
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74AC843 bảng dữ liệu(HTML) 2 Page - National Semiconductor (TI) |
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2 / 10 page ![]() Functional Description The ’AC’ACT843 consists of nine D-type latches with TRI-STATE outputs The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH This allows asyn- chronous operation as the output transition follows the data in transition On the LE HIGH-to-LOW transition the data that meets the setup times is latched Data appears on the bus when the Output Enable (OE) is LOW When OE is HIGH the bus output is in the high impedance state In addition to the LE and OE pins the ’AC’ACT843 has a Clear (CLR) pin and a Preset (PRE) pin These pins are ideal for parity bus interfacing in high performance systems When CLR is LOW the outputs are LOW if OE is LOW When CLR is HIGH data can be entered into the latch When PRE is LOW the outputs are HIGH if OE is LOW Preset overrides CLR Function Tables Inputs Internal Outputs Function CLR PRE OE LE D Q O H H H H L L Z High Z H H H H H H Z High Z H H H L X NC Z Latched H H L H L L L Transparent H H L H H H H Transparent H H L L X NC NC Latched H L L X X H H Preset L H L X X L L Clear L L L X X H H Preset L H H L X L Z ClearHigh Z H L H L X H Z PresetHigh Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance NC e No Change Logic Diagram TLF9800 – 5 2 |
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