AD2S1210WDSTZ datasheet(29/37 Pages) AD

29 / 37 page

AD2S1210

Rev. A | Page 28 of 36

SERIAL INTERFACE

The serial interface is selected by holding the SOE pin low. The

AD2S1210 serial interface consists of four signals: SDO, SDI,

WR/FSYNC, and SCLK. The SDI is used for transferring data

into the on-chip registers whereas the SDO is used for accessing

data from the on-chip registers, including the position, velocity,

and fault registers. SCLK is the serial clock input for the device,

and all data transfers (either on SDI or SDO) take place with

respect to this SCLK signal. WR/FSYNC is used to frame the

data. The falling edge of WR/FSYNC takes the SDI and SDO

lines out of a high impedance state. A rising edge on WR/FSYNC

returns the SDI and SDO to a high impedance state. The CS input

is not required for the serial interface and should be held low.

SDO Output

In normal mode of operation, data is shifted out of the device as

a 24-bit word under the control of the serial clock input, SCLK.

The data is shifted out on the rising edge of SCLK. The timing

diagram for this operation is shown in Figure 32.

SDI Input

The SDI input is used to address the on-chip registers and as a

daisy-chain input in configuration mode. The data is shifted

into the part on the falling edge of SCLK. The timing diagram

for this operation is shown in Figure 32.

Writing to the AD2S1210

The on-chip registers of the AD2S1210 can be accessed using

the serial interface. To write to one of the registers, the user

must first place the AD2S1210 into configuration mode using

the A0 and A1 inputs. The 8-bit address should be written to

the AD2S1210 using the SDI pin and latched using the rising

edge of the WR/FSYNC input. The data can then be presented on

the SDI pin and again latched into the part using the WR/FSYNC

input. The MSB of the 8-bit write indicates whether the 8-bit

word is a register address, MSB set high, or the data to be written,

MSB set low.

shows the timing specifications to follow

when writing to the configuration registers.

Figure 33

Reading from the AD2S1210 in Configuration Mode

To read back data stored in one of the on-chip registers, including

the fault register, the user must first place the AD2S1210 into

configuration mode using the A0 and A1 inputs. The 8-bit

address of the register to be read should then be written to the

part, as described in the Writing to the AD2S1210 section.

This transfers the relevant data to the output register.

In configuration mode, the output shift register is eight bits

wide. Data is shifted out of the device as an 8-bit word under

the control of the serial clock input, SCLK. The timing diagram

for this operation is shown in Figure 34. When reading back

data from any of the read/write registers (see Table 10), the 8-bit

word consists of the seven bits of data in the relevant register,

D6 to D0, and an error bit, D7. If the error bit is returned high,

this indicates that the data read back from the device does not

match the configuration data written to the device in the previous

write cycle.

To read back the angular position or velocity data while in

configuration mode, a falling edge of the SAMPLE input is

required to update the information in the position and velocity

registers.

Reading from the AD2S1210 in Normal Mode

To read back position or velocity data from the AD2S1210, the

information stored in the position and velocity registers should

first be updated using the SAMPLE input. A high-to-low

transition on the SAMPLE input transfers the data from the

position and velocity integrators to the position and velocity

registers. The fault register is also updated on the high-to-low

transition of the SAMPLE input. The status of the A0 and A1

inputs determines whether the position or velocity data is

transferred to the output register.

In normal mode, the output shift register is 24 bits wide. The 24-bit

word consists of 16 bits of angular data (position or velocity data)

followed by the 8-bit fault register data. Data is read out MSB

first (Bit 23) on the SDO pin. Bit 23 through Bit 8 correspond to

the angular information. The angular position data format is

unsigned binary, with all 0s corresponding to 0 degrees and all

1s corresponding to 360 degrees − l LSB. The angular velocity data

format is twos complement binary, with the MSB representing the

rotation direction. Bit 7 through Bit 0 correspond to the fault

information. If the user does not require the fault information,

the WR/FSYNC can be pulled high after the16th SCLK rising edge.

Clearing the Fault Register

The LOT pin and/or the DOS pin of the AD2S1210 are taken

low to indicate that a fault has been detected. The AD2S1210 is

capable of detecting eight separate fault conditions. To determine

which condition triggered the fault indication, the user is required

to enter configuration mode and read the fault register. To reset

the fault indicators, an additional SAMPLE pulse is required.

This ensures that any faults that may occur between the initial

sampling and subsequent reading of the fault register are captured.

Therefore, to read and clear the fault register, the following

sequence of events is required:

A high-to-low transition of the SAMPLE input.

Hold the SAMPLE input low for t16 ns and then it can be

returned high.

Put the AD2S1210 into configuration mode, that is, A0 and

A1 are both set to logic high.

Read the fault register as described in the Reading from the

AD2S1210 in Configuration Mode section.

A second high-to-low transition of the SAMPLE input

clears the fault indications on the DOS and/or LOT pins.

Note that in the event of a persistent fault, the fault indicators

are reasserted within the specified fault time latency.

AD2S1210WDSTZ bảng dữ liệu(PDF) 29 Page - Analog Devices

AD2S1210WDSTZ bảng dữ liệu(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

bảng dữ liệu tải về

Link URL