AD2S1210CSTZ datasheet(20/37 Pages) AD

20 / 37 page

AD2S1210

Rev. A | Page 19 of 36

48 47 46 45 44 43 42 41 40 39 38 37

CLKIN

DVDD

DGND

XTALOUT

13 14 15 16 17 18 19 20 21 22 23 24

AD2S1210

20pF

8.192

MHZ

4.7µF

10nF

10µF

4.7µF

10nF

BUFFER

CIRCUIT

BUFFER

CIRCUIT

10nF

VDRIVE

4.7µF

Figure 27 shows a suggested buffer circuit. Capacitor C1 may be

used in parallel with Resistor R2 to filter out any noise that may

exist on the EXC and EXC outputs. Care should be taken when

selecting the cutoff frequency of this filter to ensure that phase

shifts of the carrier caused by the filter do not exceed the phase

lock range of the AD2S1210.

The gain of the circuit is

))

(

)

(

Gain

Carrier

−

(7)

and

REF

OUT

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛

−

⎟

⎠

⎞

⎜

⎝

⎛

⎟

⎠

⎞

⎜

⎝

⎛ +

(8)

where:

ω is the radian frequency of the applied signal.

VREF, a dc voltage, is set so that VOUT is always a positive value,

eliminating the need for a negative supply.

12V

EXC/EXC

(VIN)

(VREF)

VOUT

AD8662

Figure 26. Connecting the AD2S1210 to a Resolver

In this recommended configuration, the converter introduces a

VREF/2 offset in the SIN, SINLO, COS, and COSLO signal outputs

from the resolver. The sine and cosine signals can each be

connected to a different potential relative to ground if the sine

and cosine signals adhere to the recommended specifications.

Note that because the EXC and EXC outputs are differential,

there is an inherent gain of 2×.

Figure 27. Buffer Circuit

A separate screened twisted pair cable is recommended for the

analog input pins, SIN, SINLO, COS, and COSLO. The screens

should terminate to either REFOUT or AGND.

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