AD9993BBCZ datasheet(35/57 Pages) AD

tên linh kiện	AD9993BBCZ

Giải thích chi tiết về linh kiện	Integrated Mixed-Signal Front End

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AD9993

Data Sheet

Rev. A | Page 34 of 56

LVDS TX CONTROL REGISTER

Address: 0x014, Reset: 0x00, Name: FLEX_OUTPUT_ADJUST

Table 19. Bit Descriptions for FLEX_OUTPUT_ADJUST

Bits

Bit Name

Description

Reset

Access

[7:5]

LVDS_BIAS_DAC

Sets LVDS output swing.

0x0

000 = 200 mV.

001 = 227 mV.

010 = 257 mV.

011 = 282 mV.

100 = 296 mV.

101 = 330 mV.

110 = 350 mV.

111 = 372 mV.

[4:2]

LVDS_BG_TRIM

Band gap trim for LVDS Tx DOUTxx_P and DOUTxx_N pins.

0x0

[1:0]

LVDS_DRIVE

Output LVDS drive current.

0x0

00 = 1 mA output drive current (default).

01 = 2 mA output drive current.

10 = 3 mA output drive current.

11 = 4 mA output drive current.

VREF CONTROL REGISTER

Address: 0x016, Reset: 0x00, Name: FLEX_VREF

Table 20. Bit Descriptions for FLEX_VREF

Bits

Bit Name

Description

Reset

Access

[4:0]

VREF_FS_ADJ

Main reference full-scale VREF adjustment.

0x0

01111 = internal 2.087 V p-p.

…

00001 = internal 1.772 V p-p.

00000 = internal 1.75 V p-p.

11111 = internal 1.727 V p-p.

…

10000 = internal 1.383 V p-p.

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