MFC2000 datasheet(129/426 Pages) ETC

129 / 426 page

Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

5-3

ext_pdsel_padn

int_pwrdwn_sel

sia_pwr_down1

sia_pwr_down2

pwrdwn_padn

Figure 5-2. Power-down Select Logic

5.1.1

Battery Power Reset

Battery Power Reset is generated when BATRSTn (as shown at lower left in Figure 5-1) is driven low, and

initializes the MFC2000 when battery power is first applied, as well as forcing a Prime Power Reset if VDD is

present. As long as battery power is maintained, there is no need to reactivate this reset. If the system design

does not utilize the MFC2000's battery power features, this reset should be tied to PWRDWNn and be activated

upon system power initialization.

Battery backup system requirements are undefined when battery power is first applied. Consequently, BATRSTn

disables the battery backup control for DRAM and disables SRAM by resetting the BackupConfig register, and

inhibits CPU access to this register via the (internal) lockout signal. The disabling of battery backup controls tri-

states the associated output control signals (i.e., CS[0]n for SRAM, and CASOn[1:0]n, CASEn[1:0], RASn[1:0],

and DWRn for DRAM, as shown at lower right in Figure 5-1.

Note:

The proper off-state logic level for battery backed-up devices external to the MFC2000

must be maintained by external pull-up/pull-down resistors on the appropriate MFC2000 pins.

BATRSTn has a Schmitt trigger input buffer to allow the use of an external RC circuit to generate a reset.

5.1.2

Prime Power Reset

Prime Power Reset occurs when PWRDWNn (shown at upper left in Figure 5-1) is driven low while prime power

is applied. There are two Prime Power Reset operating modes, one for VDD power on and one for VDD power

off.

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