MFC2000 datasheet(104/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-74

Conexant

100723A

4.6.3

Timing

All accesses can be performed from zero to seven wait states. The number of wait states is programmable in the

FlashCtrl register. During write operations, if one to seven wait states is used, the EarlyOff option must be set in

the FlashCtrl register. The EarlyOff option is ignored with zero wait state.

Wait states are generated to accommodate slow memory devices, for more details of how the control signals are

changed with an inserted wait state, refer to the timing diagram Figure 4-31.

•

NAND-Type flash For this type of flash, addresses and data are passed through the external data bus.

During read operations, the device selection is one of the two Flash Chip Select signals FCSn[1:0], FRDn is

the Flash Read Enable signal from the bus interface. FCLE and FALE must be low (inactive) during reads.

For zero wait state access, FWRn and FRDn are only half SIUCLK cycle (like RDn and WRn of the normal

bus operation).

During program/erase operations, the device selection is one of the FCSn[1:0] signals. Command, address

and data are all written through the external data bus. The Flash Command Latch Enable (FCLE ) and the

Flash Address Latch Enable (FALE) signals are the controls for writing to the Command or the Address

•

NOR-Type Flash Accesses are performed using normal bus operations.

During program/erase operations, the device selections are the two Flash Chip Select signals FCSn[1:0],

addresses are latched on the falling edge of the Flash Write Enable signal WREn/WROn, and data is latched

on the rising edge of WREn/WROn.

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