MFC2000 datasheet(389/426 Pages) ETC

389 / 426 page

Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

24-3

24.1 Countach Imaging DSP Subsystem

24.1.1 Description

The Countach Imaging DSP Subsystem is mainly responsible for monochrome and color image processing and

JPEG compression and decompression. The Countach Imaging DSP subsystem contains the Countach core,

data RAM and ROM, program RAM and program ROM, scratch pad, and DMA channels.

24.1.2 Countach Imaging DSP Subsystem Memory

Program Memory:

•

× 40 RAM

•

ROM for program initialization

Data RAM:

•

× 16 register file RAM

•

× 16 DMA-accessible RAM

•

× 16 RAM

•

8K x 16 ROM

24.1.3 Countach Imaging DSP Subsystem DMA

Data DMA:

•

4 channels

•

DMA accesses are made via the scratch pad interface

•

Countach Imaging DSP controls which bank DMA transfers occur in – DMA channel does not automatically

switch after completion of a block transfer

•

Consecutive DMA cycles must be able to occur at a minimum rate of 6 Countach clocks per transfer

Program DMA:

•

Minimum of 1 channel

•

DMA accesses are made via the scratch pad interface

•

Consecutive DMA cycles must be able to occur at a minimum rate of 6 Countach clocks per transfer

•

An entire instruction is formed by transferring it in three 16-bit segments to scratch pad addresses 0x1b0,

0x1b1, and 0x1b2

24.1.4 Running Frequency

The Countach Imaging DSP Subsystem operates at either 87.5MHz or 100 MHz. It is configurable through the

CLK_CONFIG[2] signal which is muxed on the ROMCSn pin.

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