MFC2000 datasheet(334/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

17-12

Conexant

100723A

DMA FIFO Registers

There will be two 4 half word FIFOs used for forward and reverse DMA transfers. The FIFO locations will be

accessed from CPU as well as DMA. The address locations for the forward DMA FIFO will be 01FF8220 to

01FF822F. The address locations for the reverse FIFO will be 01FF8230 to 01FF823F.

Output data FIFO halfword[3:0] for the data to the external memory (the forward direction) (for DMA

channel 11):

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

Parallel Port Output

Data FIFO

(PIOOutFIFOx)

data

bit 15

data

bit 14

data

bit 13

data

bit 12

data

bit 11

data

bit 10

data

bit 9

data

bit 8

Rst Value

00h

Read

Value 00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

Parallel Port Output

Data FIFO

(PIOOutFIFOx)

data

bit 7

data

bit 6

data

bit 5

data

bit 4

data

bit 3

data

bit 2

data

bit 1

data

bit 0

Rst Value

00h

Read

Value 00h

•

Address assignment for Output FIFO halfword[3:0]

The Input FIFO halfword

The register name

Address

Output FIFO halfword 3

PIOOutFIFO3

01FF8227-26

Output FIFO halfword 2

PIOOutFIFO2

01FF8225-24

Output FIFO halfword 1

PIOOutFIFO1

01FF8223-22

Output FIFO halfword 0

PIOOutFIFO0

01FF8221-20

Output data FIFO Holding Register for the data to the external memory (the forward direction)

(for DMA channel 11):

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

Parallel Port Output

Data FIFO Holding

(PIOOutHold)

$01FF8229

data

bit 15

data

bit 14

data

bit 13

data

bit 12

data

bit 11

data

bit 10

data

bit 9

data

bit 8

Rst Value

xxh

Read

Value xxh

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

Parallel Port Output

Data FIFO Holding

(PIOOutHold)

$01FF8228

data

bit 7

data

bit 6

data

bit 5

data

bit 4

data

bit 3

data

bit 2

data

bit 1

data

bit 0

Rst Value

00h

Read

Value 00h

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