MFC2000 datasheet(326/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

17-4

Conexant

100723A

17.4 Register Description

Parallel Port Control Register

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Parallel Port Control

Reg.

(PIOCtrl)

$01FF8201

(Not Used)

TRIZN

PPIRSTN

MODE

RFULL

(R)

FFULL

(R)

Rst. Value

xx000000b

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Parallel Port

Control Reg.

(PIOCtrl)

$01FF8200

RLD

(R)

ABRT

PDOE

(R)

ERRC

MODE

DFIL

Rst. Value

00h

Read Value

00h

DFIL

Digital Filter

This 2 bit field controls the number of clocks of digital filtering to be

applied on the four host control signal inputs, SLCTINn, STROBEn,

AUTOFDn, and INITn. From 0 to 3 clocks of digital filtering may be

selected.

MODE

Mode

This 4 bit field(bits 11,10,3,2) selects and enables a hardware

handshaking mode for forward data transfers.

MODE

Direction

Function

Disable

Fwd

Compatibility mode

Fwd

ECP-fwd without RLE mode

Fwd

ECP-fwd with RLE mode

Rev

Nibble mode

Rev

Byte mode

Rev

ECP-rev mode

Rev

Dribble mode

8-15

Reserved

Error Cycles

This bit is used to execute an error cycle when in compatibility mode

(mode 1). When set, ERRC immediately forces the BUSY pin high. If

ERRC is set when a compatibility mode handshake sequence is in

process, the BUSY remains high beyond the end of the cycle. ERRC

does not affect an ACKn pulse that is already active, but does prevent

an ACKn pulse if it is about to be generated. While ERRC is set,

software may set or clear SEL, PERR, and NFLT in the Parallel Port

Interface Register. When ERRC is cleared, the PPI generated an

ACKn pulse and tries to lower BUSY to conclude the error cycle. If,

however, FBSY is set, BUSY remains high until FBSY is cleared.

When MODE is set to any value except 1, setting ERRC has no effect.

Setting MODE to 1 when ERRC is already set causes the handshake

controller to immediately begin an error cycle.

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