MFC2000 datasheet(302/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

16-4

Conexant

100723A

Bit 15-0:

Not used

Writing any value to this register causes a push or pop of data through

the FIFO data port and the FIFO Quad Halfword 1-4 registers. The

FIFO operation depends on the direction of data flow. If system bus

(CPU or DMA) is writing (filling) the FIFO, data is transferred from the

FIFO data port register to the FIFO Quad Halfword 1 register,

simultaneously with data transfer from Quad Halfword 1 to Quad

Halfword 2, Quad Halfword 2 to Quad Halfword 3, and Quad Halfword

3 to Quad Halfword 4, with the original data of Quad Halfword 4 being

lost. If the system bus is reading (emptying) the FIFO, data is

transferred from the FIFO Quad Halfword 1 register to the FIFO data

port register, simultaneously with data transfer from Quad Halfword 2

to Quad Halfword 1, Quad Halfword 3 to Quad Halfword 2, and Quad

Halfword 4 to Quad Halfword 3, with the contents of Quad Halfword 4

becoming indeterminate.

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

USBEP2Fifo1

(R/W)

$01FF85A1

EP2 Bulkout Half Word 1

Rst. Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

USBEP2Fifo1

(R/W)

$01FF85A0

EP2 Bulkout Half Word 1

Rst. Value

00h

Read Value

00h

Bits 15-0:

Endpoint 2 FIFO Quad Half word 1

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

USBEP2Fifo2

(R/W)

$01FF85A3

EP2 Bulkout Half Word 2

Rst. Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

USBEP2Fifo2

(R/W)

$01FF85A2

EP2 Bulkout Half Word 2

Rst. Value

00h

Read Value

00h

Bits 15-0:

Endpoint 2 FIFO Quad Half word 2

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