MFC2000 datasheet(295/426 Pages) ETC

295 / 426 page

Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

15-15

After receiving the Stop bit, when FIFO mode is disabled, the SERIRQ and the RxBufFull will both rise to

a logic 1. RxBufFull and the SERIRQ will be cleared by reading of the SASData Register.

LSB

Stop Bit

MSB

Rd SerData

Start Bit

SASRXD

SASCs

RxBufFull

Figure 15-7. Asynchronous Receiver Byte Timing – FIFO mode disabled

When FIFO-mode is enabled, after receiving the stop bit, the SERIRQ and the RxBufFull will change to a logic 1

only if the receive FIFO becomes full as a result of adding that last byte. Both the interrupt and RxBufFull bit will

be cleared when the SASData Register is read.

SASCSn

SASRXD

RxFIFOEnb

Rxload

RxBufFull

SAS DATA RD

15 16

bytes

Figure 15-8. Asynchronous Receiver Byte Timing – FIFO mode enabled

The last feature of the FIFO mode is the timeout interrupt. In normal cases, the receive FIFO only causes an

interrupt when it is completely full. However, in the case where less than 16 bytes were received and no more

bytes are being sent to the SASIF, the timeout function tells the ARM that no data has been received within the

required amount of time, so a RxTimeoutIRQ occurs. The time required to cause this interrupt is based on the

baud rate and is 4 times the ammount of time that it would take to send one byte of data into the RxShift Register.

So if no byte is transferred from the RxShift Register to the receive FIFO, nor is any bit shifted onto the RxShift

SASCSn

SASRXD

RxFIFOEnb

Rxload

TxBaudend

SAS DATA RD

RxTimerElapsed

123

32 beats without a Rxload

Figure 15-9. Asynchronous Receiver FIFO Timeout



FIFO Mode Enabled

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