HD74AC datasheet(46/52 Pages) HITACHI

46 / 52 page

Design Considerations

0.1"

0.04"

VCC

1/16" Glass Epoxy

a) 50

Ω VCC

Impedance

Ground Plane

Gnd

VCC

b) 100

Ω VCC

Impedance

1/16 Board

Gnd

VCC

c) 68

Ω VCC

Impedance

1/16 Board

Gnd

VCC

d) 100

Ω VCC

Impedance

1/16 Board

Gnd

VCC

e) 2

Ω VCC

Impedance

032

Epoxy Glass

Figure 17 Power Distribution Impedances

3.9 V

78 mA

4 ns

Ground

Plane

Worst-Case Octal Drain = 8

× 78 mA = 0.624 Amp.

Buffer Output Sees Net 50

Ω Load.

Ω Load Line on I

OH-VOH Characteristic

Shows Low-to-High Step of Approx. 3.9 V

0 V

IOH

VOUT

100

Ω

Buffer

Data Bus

1 of 8

100

Ω

Figure 18 Octal Buffer Driving a 100

Ω Bus

Q = CV

I = C

∆V/∆t

C = I

∆t/∆V

∆t = 4 × 10–9

I = 0.75 A

VCC Bus

ZCC

Bypass Capacitors

Specify VCC Droop = 0.1 V max.

C =

Select CB ≥ 0.047 µF

= 25

× 10–9 = 0.025 µF

0.1

0.624

× 4 × 10–9

VCC

Place one decoupling capacitor adjacent to each package driving any transmission line and distribute others

evenly thoughout the logic. One capacitor per three packages.

Figure 19 Formula for Calculating Decoupling Capacitors

In this example, if the V

CC droop is to be kept below 0.1 V and the edge rate equals 4 ns, a 0.025 µF

capacitor is needed.

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