CS62180B datasheet(14/50 Pages) CIRRUS

14 / 50 page

SLC-96

® Timing

Figure A6 of the Application Section, shows the

SLC-96

® superframe structure. Note that in Fig-

ure A6, the first C bit (C1) resides in frame 12.

A low to high transition of TMSYNC identifies

Frame 1 of Figure A6.

Frame and multiframe timing is output on

TCHCLK, TMO, TSIGSEL, TSIGFR and

TLCLK. TSIGSEL can be used to identify the

location of the DL bits. The TSIGSEL output is

high during frames 58 to 11, and is low during

frames 12 to 57.

When TSIGSEL is low, the

CS62180B accepts DL bits on TLINK at a 4

kHz rate, The DL bits which are input on

TLINK are: C1-C11, DC, DC, DC, M1-M3, A1,

A2, S1-S4. "DC" signifies "don’t care" bits. The

DC-bit positions correspond to the spoiler bits.

The CS62180B internally generates the spoiler

bits. The data input on TLINK in the DC posi-

tion is ignored by the CS62180B. TLCLK is a 4

kHz clock for the TLINK input. TLCLK goes

high during odd frames.

TMO transitions high at the beginning of every

12th frame. TSIGFR goes high during signaling

frames (every 6 frames). The rising edge of

TMO identifies the 6

th frame, and the falling

edge of TMO identifies the 12

th frame for exter-

nal multiplexing of signaling channels.

See

Figure 8 for timing diagram.

Frame

TMSYNC

TFSYNC

TMO

TSIGSEL

TSIGFR

TLCLK

2 3 45 67

18 910 11 12

2 3 456 7

8 9

14 15 16 17

19 20 21 22 23 24

Figure 7. 193E Multiframe Transmit Timing

Frame

TMSYNC

TFSYNC

TMO

TSIGSEL

TSIGFR

TLCLK

2 34 5 6 7

89 10 11 12

2 34 5 67

18 9 10 11 12

234 5 6 7

18 9

ABA

Figure 6. 193S Multiframe Transmit Timing

CS62180B

DS225PP2

CS62180B bảng dữ liệu(PDF) 14 Page - Cirrus Logic

CS62180B bảng dữ liệu(HTML) 14 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

bảng dữ liệu tải về

Link URL