ADE9000ACPZ datasheet(38/73 Pages) AD

38 / 73 page

Data Sheet

ADE9000

Rev. A | Page 37 of 72

ACCESSING ON-CHIP DATA

SPI PROTOCOL OVERVIEW

The ADE9000 has an SPI-compatible interface, consisting of

four pins: SCLK, MOSI, MISO, and SS. The ADE9000 is always

an SPI slave; it never initiates SPI communication. The SPI

interface is compatible with 16-bit and 32-bit read/write operations.

The maximum serial clock frequency supported by this interface is

20 MHz.

The ADE9000 provides SPI burst read functionality on certain

registers and the waveform buffer that allows multiple registers

to be read after sending one CMD_HDR.

3 2

ADDR[11:0]

R/W

xxx

READ = 1

WRITE = 0

DON’T CARE BITS

ADDRESS TO BE ACCESSED

Figure 72. Command Header, CMD_HDR

The ADE9000 SPI port calculates a 16-bit cyclic redundancy

check (CRC-16) of the data sent out on its MOSI pin so that the

integrity of the data received by the master can be checked. The

CRC of the data sent out on the MOSI pin during the last register

read is offered in a 16-bit register, CRC_SPI, and can be

appended to the SPI read data as part of the SPI transaction.

ADDITIONAL COMMUNICATION VERIFICATION

REGISTERS

The ADE9000 includes three registers that allow SPI operation

verification. The LAST_CMD (Address 0x4AE), LAST_DATA_16

(Address 0x4AC), and LAST_DATA_32 (Address 0x423) registers

record the received CMD_HDR and the last read or transmitted

data.

CRC OF CONFIGURATION REGISTERS

The configuration register CRC feature in the ADE9000

monitors certain external and internal register values. It also

optionally includes 15 registers that are individually selectable in

the CRC_OPTEN register. The result is stored in the CRC_RSLT

the monitored registers change the value of the CRC_RSLT

CONFIGURATION LOCK

The configuration lock feature prevents changes to the ADE9000

configuration. To enable this feature, write 0x3C64 to the

WR_LOCK register. To disable the feature, write 0x4AD1.

To determine whether this feature is active, read the

WR_LOCK register, which reads as 1 if the protection is

enabled and 0 if it is disabled.

When this feature is enabled, it prevents writing to addresses

from Address 0x000 to Address 0x073 and Address 0x400 to

Address 0x4FE.

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