AD5252EVAL datasheet(9/28 Pages) AD

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AD5251/AD5252

Rev. 0 | Page 9 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTION

AD0

SDA

VDD

AD1

VSS

SCL

DGND

AD5251/

AD5252

TOP VIEW

(Not to Scale)

Figure 2. AD5251/AD5252 in TSSOP-14

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

VDD

Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply,

where VDD – VSS ≤ 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to

EEMEM.

AD0

I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252s to be addressed.

Write Protect, Active Low. VWP ≤ VDD + 0.3 V.

Wiper Terminal of RDAC1. VSS ≤ VW1 ≤ VDD.1

B Terminal of RDAC1. VSS ≤ VB1 ≤ VDD.1

A Terminal of RDAC1. VSS ≤ VA1 ≤ VDD.1

SDA

Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock edges. MSB loaded

first. Open-drain MOSFET requires pull-up resistor.

VSS

Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where VDD – VSS ≤

+5.5 V. If VSS is used, other than grounded, in dual supply, VSS must be able to sink 35 mA for

26 ms when storing data to EEMEM.

SCL

Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. VSCL ≤

(VDD + 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power.

DGND

Digital Ground. Connect to system analog ground at a single point.

AD1

I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252s to be addressed.

A Terminal of RDAC3. VSS ≤ VA3 ≤ VDD.1

B Terminal of RDAC3. VSS ≤ VB3 ≤ VDD.1

W Terminal of RDAC3. VSS ≤ VW3 ≤ VDD.1

1 For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.

I2C INTERFACE TIMING DIAGRAM

SCL

SDA

t10

Figure 3. I2C Timing Diagram

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