VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC838

3.2Gb/s

36x37 Crosspoint Switch

G52351-0, Rev 3.0

Page 9

02/12/01

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I/O Equivalent Circuits

Input Termination

The high-speed inputs of the VSC838 are internally terminated by a 100

Ω impedance between true and

complement inputs. Termination resistors are isolated from each other on-chip. The termination will self-bias to

+2.0V (nominal) for AC-coupled applications. The ITC pin enables direct interconnection of multiple VSC838

terminations to act as loads for an open-drain or open-collector differential output.

Table 7: Allowed Input Termination Schemes

Table 8.

Table 8: Additional Current and Power

Type

Description

Comments

1

AC-coupled input

Tie ITC LOW, 100

Ω differential input termination,

input self-biased

2

DC-coupled from open-drain CML

Tie ITC HIGH, terminations acts as 50

Ω load to V

CC

3

DC-coupled from back-terminated 2.5V CML

Tie ITC HIGH, terminations acts as 50

Ω load to V

CC

4

DC-coupled from back-terminated 2.5V CML

Tie ITC LOW, 100

Ω differential termination

(preferred over Type 3)

5

DC-coupled from back-terminated 3.3V LV-PECL

Tie ITC LOW, 100

Ω differential termination

Parameter

Description

Min

Typ

Max

Units

Conditions

Additional ICC current when receiving DC-

Coupled CML (ITC = HIGH)

180

mA

Additional power dissipated on-chip for

DC terminating CML at inputs

0.180

W

PAD

PAD

50

50

H/S Input Equivalent Circuit

H/S Output Equivalent Circuit

PAD

PAD

50

50

VCC

ITC

TERM_CTRL

DRIVE_CTRL