Teq

SOA

C,MAX

175 C

96.3 C

I

64.5 ms,T

1.12 A

0.59 A

175 C

25 C

q

q

u

q

q

0.52

0.25

SOA

I

64.5 ms, 25 C

3.16 A

ms

64.5 ms

1.12 A

q

u

u

SOA

2

0.25

m

0.25

2

I

t

1 A

a

3.16 A

ms

t

100 ms

u

SOA

1

SOA

2

1

2

1.8 A

ln

ln (I

t

/ I

t

)

1 A

m

0.25

10 ms

ln t / t

ln

100 ms

§

·

¨

¸

©

¹

§

·

¨

¸

©

¹

21

TPS23521

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Finally, the FET SOA needs to be derated based on the maximum case temperature as shown below. Note that

the FET can handle 0.59A, while it will have 0.4A during start-up. Thus there is a lot of margin during this test

condition.

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A similar approach should be taken to compute the FETs SOA capability during a Hot Short and start into short.

As shown in the following figure, during a start into short the gate is coming up very slowly due to a large

capacitance tied to the gate through the SS pin. Thus it is more stressful than a Hot Short and should be used for

worst case SOA calculations. To compare the FET stress during start-up into short to the SOA curves the stress

needs to be approximated as a square pulse as showing in the figure below. In this example, the stress is

approximated with a 1.1ms (Teq), 1.5A, 60V pulse. The FET can handle 6A, 60V for 1ms and 1.8A, 60V for

10ms. Using approximation and temp derating as shown earlier, the FET's capability can be computed as 3A,

60V, for 1.1ms at 96°C. 3A is significantly larger than 1.5A implying good margin.

Figure 13. Teq During a Start Into a Short