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SCANSTA111 bảng dữ liệu(PDF) 17 Page - National Semiconductor (TI) |
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SCANSTA111 bảng dữ liệu(HTML) 17 Page - National Semiconductor (TI) |
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17 / 29 page  Register Descriptions (Continued) TABLE 7. Mode Register Control of LSPN (Continued) Mode Register(s) Scan Chain Configuration (if unparked) MR0: X000X001 TDI B → Register → LSP0 → PAD → TDOB MR0: X000X010 TDI B → Register → LSP1 → PAD → TDOB MR0: X000X011 TDI B → Register → LSP0 → PAD → LSP1 → PAD → TDOB MR0: X000X100 TDI B → Register → LSP2 → PAD → TDOB MR0: X000X101 TDI B → Register → LSP0 → PAD → LSP2 → PAD → TDOB MR0: X000X110 TDI B → Register → LSP1 → PAD → LSP2 → PAD → TDOB MR0: X000X111 TDI B → Register → LSP0 → PAD → LSP1 → PAD → LSP2 → PAD → TDOB MR0: X010X000 TDI B → Register → LSP3 → PAD → TDOB MR0: X010X001 TDI B → Register → LSP0 → PAD → LSP3 → PAD → TDOB MR0: X010X010 TDI B → Register → LSP1 → PAD → LSP3 → PAD → TDOB MR0: X010X011 TDI B → Register → LSP0 → PAD → LSP1 → PAD → LSP5 → PAD → TDOB MR0: X010X100 TDI B → Register → LSP2 → PAD → LSP3 → PAD → TDOB ... ... MR0: X110X111 TDI B → Register → LSP0 → PAD → LSP1 → PAD → LSP2 → PAD → LSP3 → PAD → LSP4 → PAD → TDO B MR0: X000X000 MR1: XXXXX001 (Note 10) TDI B → Register → LSP5 → PAD → TDOB MR0: X000X001 MR1: XXXXX001 (Note 10) TDI B → Register → LSP0 → PAD → LSP5 → PAD → TDOB MR0: X000X010 MR1: XXXXX001 (Note 10) TDI B → Register → LSP1 → PAD → LSP5 → PAD → TDOB ... ... MR0: X110X111 MR1: XXXXX001 (Note 10) TDI B → Register → LSP0 → PAD →→ LSP1 → PAD → LSP2 → PAD → LSP3 → PAD → LSP4 → PAD → LSP 5 → PAD → TDOB MR0: X000X000 MR1: XXXXX010 (Note 10) TDI B → Register → LSP6 → PAD → TDOB ... ... MR0: X110X111 MR1: XXXXX111 (Note 10) TDI B → Register → LSP0 → PAD → LSP1 → PAD → LSP2 → PAD → LSP3 → PAD → LSP4 → PAD → LSP 5 → PAD → LSP6 → PAD → LSP7 → PAD → TDOB MR0: XXX1XXXX MR1: XXXXXXXX (Note 10) TDI B → Register → TDOB (Loopback) Note 10: Mode Register1 is only available in the HDL version (up to eight LSPs). The Silicon version has three LSPs and uses Mode Register0 only. Note 11: In a device with 8 LSPs there are 28 possible LSPN configurations: No LSPs, each individual LSP, combinations of 2 to 7 LSPs, and all 8 LSPs. TABLE 8. Test Clock Configuration Bit 3 LSP n TCK n 1 Parked Stopped 0 Parked Free-running 1 Unparked Free-running 0 Unparked Free-running X Parked-TLR Stopped after 512 clock pulses Bit 3 is normally set to logic 0 so that TCK n is free-running when the local scan ports are parked in the Parked-RTI, Parked-Pause-DR or Parked-Pause-IR state. When the local ports are parked, bit 3 can be programmed with logic 1, forcing all of the LSP TCK n’s to stop. This feature can be used in power sensitive applications to reduce the power consumed by the test circuitry in parts of the system that are not under test. When in the Parked-TLR state, TCK n is gated (stopped) after 512 clock pulses have been received on TCK B independent of the bit 3 value. Bit 7 is a status bit for the TCK counter. Bit 7 is only set (logic 1) when the TCK counter is on and has reached terminal www.national.com 17 |
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