Datasheet: PECL_RX - C35

Revision B, 10.09.02

Page5fo6

APPLICATION

!

High Speed Backplane Driver

!

Complementary Clock Drivers

!

Level Translator

!

System Interconnects

!

ATM Applications

!

SDH Applications

!

High-Resolution Imaging Applications

!

Laser Printers

!

Digital Copiers

µF

1

µF

1

VDDA

VSSA

22pF

100pF

Ω

50

Ω

3)

µF

1

22pF

100pF

VDDA

VT

-

2V

VREF

180pF

1nF

50

Ω

50

+

external

chip internal

1) 4)

VDDA

VSS

4)

3)

VSSA

4)

3)

7)

7)

7)

5)

complementary

CMOS signals

(to digital core)

VDD

22pF

100pF

DATA

transmission lines

from transmitter

DATAN

VT

VT

1)

Each power pin must have its own set of blocking capacitors.

2)

An external reference must be used.

3)

VSSA and VSS must be connected on the PCB level.

4)

The two power pads can be bonded to one package pin (double bonding).

5)

Two more PECL_RX cells can be driven with IREFxx of the PERXBIAS cell. If an output IREFxx is not used it must be left unconnected.

6)

The PECL part of the chip has to be separated from the rest of the chip by use of snap backs (cell PWRCUT_DIG_P_SNAP_SNAP).

7)

The cells VDD3R1P and VDD3R2P are not in the standard library, they are part of the IP-block.