LM138QML datasheet(29/34 Pages) TI1

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LM138QML

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SNVSAA9 – OCTOBER 2017

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9 Power Supply Recommendations

The input supply to LM138QML must be kept at a voltage level such that its maximum input to output differential

voltage rating is not exceeded. The minimum dropout voltage must also be met with extra headroom when

possible to keep the LM138QML in regulation. TI recommends a capacitor be placed at the input to bypass

noise.

10 Layout

10.1 Layout Guidelines

Some layout guidelines must be followed to ensure proper regulation of the output voltage with minimum noise.

Traces carrying the load current must be wide to reduce the amount of parasitic trace inductance and the

feedback loop from VOUT to ADJ must be kept as short as possible. To improve PSRR, a bypass capacitor can

be placed at the ADJ pin and must be placed as close as possible to the device. In cases when VIN shorts to

ground, an external diode must be placed from VOUT to VIN to divert the surge current from the output capacitor

and protect the deice. Similarly, in cases when a large bypass capacitor is placed at the ADJ pin and VOUT shorts

to ground, an external diode must be placed from ADJ to VOUT to provide a path for the bypass capacitor to

discharge. These diodes must be placed close to the corresponding device pins to increase their effectiveness.

10.2 Layout Example

Figure 44. LM138QML Layout

LM138QML bảng dữ liệu(PDF) 29 Page - Texas Instruments