ADAU1461WBCPZ-R7 datasheet(83/89 Pages) AD

83 / 89 page

ADAU1461

Rev. 0 | Page 82 of 88

R65: Clock Enable 0, 16,633 (0x40F9)

This register disables or enables the digital clock engine for different blocks within the ADAU1461. For maximum power saving, use this

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

SLEWPD

ALCPD

DECPD

SOUTPD

INTPD

SINPD

SPPD

Table 88. Clock Enable 0 Register

Bits

Bit Name

Description

SLEWPD

Codec slew digital clock engine enable. When powered down, the analog playback path volume controls are

disabled and stay set to their current state.

0 = powered down (default).

1 = enabled.

ALCPD

ALC digital clock engine enable.

0 = powered down (default).

1 = enabled.

DECPD

Decimator resync (dejitter) digital clock engine enable.

0 = powered down (default).

1 = enabled.

SOUTPD

Serial routing outputs digital clock engine enable.

0 = powered down (default).

1 = enabled.

INTPD

Interpolator resync (dejitter) digital clock engine enable.

0 = powered down (default).

1 = enabled.

SINPD

Serial routing inputs digital clock engine enable.

0 = powered down (default).

1 = enabled.

SPPD

Serial port digital clock engine enable.

0 = powered down (default).

1 = enabled.

R66: Clock Enable 1, 16,634 (0x40FA)

This register enables Digital Clock Generator 0 and Digital Clock Generator 1. Digital Clock Generator 0 generates sample rates for the

ADCs, DACs, and DSP. Digital Clock Generator 1 generates BCLK and LRCLK for the serial port when the part is in master mode. For

maximum power saving, use this register to disable clocks that are not being used.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

CLK1

CLK0

Table 89. Clock Enable 1 Register

Bits

Bit Name

Description

CLK1

Digital Clock Generator 1.

0 = off (default).

1 = on.

CLK0

Digital Clock Generator 0.

0 = off (default).

1 = on.

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