MSP3401G datasheet(91/104 Pages) MICRONAS

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PRELIMINARY DATA SHEET

MSP 34x1G

Micronas

6.3.5. Register MODE_REG

Note: The use of this register is no longer recom-

mended. It should be used only in cases where soft-

ware compatibility to the MSP 34x0D is required.

Using the STANDARD SELECTION register together

with the MODUS register provides a more economic

way to program the MSP 34x1G.

As soon as this register is applied, the MSP 34x1G

works

the

MSP 34x0D

Manual/Compatibility

Mode. In this mode, BTSC, EIA-J, and FM-Radio are

disabled. Only MSP 34x0D features are available; the

use of MODUS and STATUS register is not allowed.

The MSP 34x1G is reset to the normal mode by first

programming the MODUS register, followed by trans-

mitting a valid standard code to the STANDARD

SELECTION register.

The register ‘MODE_REG’ contains the control bits

determining the operation mode of the MSP 34x1G in

the MSP 34x0D Manual/Compatibility Mode; Table 6–

12 explains all bit positions.

Table 6–11: AD_CV parameters for Constant Input Gain (AD_CV[7]=0)

Step

AD_CV [6:1]

Constant Gain

Gain

Input Level at pin ANA_IN1

+ and ANA_IN2+

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

3.00 dB

3.85 dB

4.70 dB

5.55 dB

6.40 dB

7.25 dB

8.10 dB

8.95 dB

9.80 dB

10.65 dB

11.50 dB

12.35 dB

13.20 dB

14.05 dB

14.90 dB

15.75 dB

16.60 dB

17.45 dB

18.30 dB

19.15 dB

20.00 dB

maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)

maximum input level: 0.14 Vpp

1) For signals above 1.4 V

pp, the minimum gain of 3 dB is switched and overflow of the A/D converter may result. Due to the

robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or

FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N ratio of about 10 dB may appear.

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