Pin Descriptions

Name

micro SMD*

Function

V

EN

A1

Enable Input Logic, Enable High

GND

B2

Common Ground

V

OUT

C1

Output voltage of the LDO

V

IN

C3

Input voltage of the LDO

MODE

A3

Power Mode Control, Active = 1, Sleep

Mode = 0

* The pin numbering scheme for the micro SMD package was revised in April, 2002 to conform to JEDEC standard. Only the pin numbers

were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering

scheme had VEN as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and MODE as pin 5.

Ordering Information

BP refers to a 0.170mm bump size with package height of 0.9mm

Output

Voltage (V)

Grade

LP3987 Supplied as 250

Units, Tape and Reel

LP3987 Supplied as 3000

Units, Tape and Reel

2.85*

STD

LP3987IBP-2.85

LP3987IBPX-2.85

* Please contact National Semiconductor for availability

BL refers to a 0.300mm bump size with package height of 0.9mm

Output

Voltage (V)

Grade

LP3987 Supplied as 250

Units, Tape and Reel

LP3987 Supplied as 3000

Units, Tape and Reel

2.85

STD

LP3987IBL-2.85

LP3987IBLX-2.85

* Please contact National Semiconductor for availability

TL refers to a 0.300mm bump size with package height of 0.6mm

Output

Voltage (V)

Grade

LP3987 Supplied as 250

Units, Tape and Reel

LP3987 Supplied as 3000

Units, Tape and Reel

2.5

STD

LP3987ITL-2.5

LP3987ITLX-2.5

2.6

STD

LP3987ITL-2.6

LP3987ITLX-2.6

2.8

STD

LP3987ITL-2.8

LP3987ITLX-2.8

2.85

STD

LP3987ITL-2.85

LP3987ITLX-2.85

3.0*

STD

LP3987ITL-3.0

LP3987ITLX-3.0

* Please contact National Semiconductor for availability

www.national.com

3