AD9601 datasheet(25/33 Pages) AD

25 / 33 page

AD9601

Rev. 0 | Page 24 of 32

Addr

(Hex)

Parameter Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default Notes/

Comments

clock

Duty cycle

stabilizer:

0 =

disabled

1 =

enabled

(default)

0x01

test_io

Reset

PN23 gen:

1 = on

0 = off

(default)

Reset

PN9 gen:

1 = on

0 = off

(default)

Output test mode:

0000 = off (default)

0001 = midscale short

0010 = +FS short

0011 = −FS short

0100 = checker board output

0101 = PN 23 sequence

0110 = PN 9

0111 = one/zero word toggle

1000 = unused

1001 = unused

1010 = unused

1011 = unused

1100 = unused

(Format determined by output_mode)

0x00

When set, the

test data is

placed on the

output pins in

place of normal

data.

ain_config

Analog

input

disable:

1 = on

0 = off

(default)

CML

enable:

1 = on

0 = off

(default)

0x00

output_mode

Interleave

output

mode:

1 =

enabled

0 =

disabled

(default)

Output

enable:

0 =

enable

(default)

1 =

disable

Output

invert:

1 = on

0 = off

(default)

Data format select:

00 = offset binary

(default)

01 = twos

complement

10 = Gray code

0x00

output_phase

Output

clock

polarity

1 =

inverted

0 =

normal

(default)

0x03

flex_output_delay

Output

delay

enable:

0 =

enable

1 =

disable

Output clock delay:

00000 = 0.1 ns

00001 = 0.2 ns

00010 = 0.3 ns

…

11101 = 3.0 ns

11110 = 3.1 ns

11111 = 3.2 ns

0x00

flex_vref

Input voltage range setting:

10000 = 0.98 V

10001 =1.00 V

10010 = 1.02 V

10011 =1.04 V

…

11111 = 1.23 V

00000 = 1.25 V

00001 = 1.27 V

…

01110 = 1.48 V

01111 = 1.50 V

0x00

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