CLC408 datasheet(5/12 Pages) NSC

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CLC408 DESIGN INFORMATION

Standard op amp circuits work with CFB op amps.

There are 3 unique design considerations for CFB:

The feedback resistor (Rf in Figures 1-3) sets

AC performance

Rf cannot be replaced with a short or a capacitor

The output offset voltage is not reduced by

balancing input resistances

The following sub-sections cover:

Design parameters, formulas and techniques

Interfaces

Application circuits

Layout techniques

SPICE model information

DC Gain (non-inverting)

The non-inverting DC voltage gain for the configuration

shown in Figure 1 is:

Figure 1: Non-Inverting Gain

The normalized gain plots in the

Typical Performance

Characteristics section show different feedback

resistors (Rf) for different gains. These values of Rf are

recommended for obtaining the highest bandwidth with

minimal peaking. The resistor Rt provides DC bias for

the non-inverting input.

For Av < 6, use linear interpolation on the nearest Av

values to calculate the recommended value of Rf. For

Av ≥ 6, the minimum recommended Rf is 200Ω.

Select Rg to set the DC gain:

DC gain accuracy is usually limited by the tolerance of

Rf and Rg.

DC Gain (unity gain buffer)

The recommended Rf for unity gain buffers is 3kΩ. Rg

is left open. Parasitic capacitance at the inverting node

may require a slight increase of Rf to maintain a flat

frequency response.

DC Gain (inverting)

The inverting DC voltage gain for the configuration

shown in Figure 2 is:

The normalized gain plots in the

Typical Performance

Characteristics section show different feedback

resistors (Rf) for different gains. These values of Rf are

recommended for obtaining the highest bandwidth with

minimal peaking. The resistor Rt provides DC bias for

the non-inverting input.

For |Av| < 6, use linear interpolation on the nearest Av

values to calculate the recommended value of Rf. For

|Av| ≥ 6, the minimum recommended Rf is 200Ω.

Figure 2: Inverting Gain

Select Rg to set the DC gain:

. At large gains,

Rg becomes small and will load the previous stage.

This can be solved by driving Rg with a low impedance

buffer like the CLC111, or increasing Rf and Rg. See

the

AC Design (small signal bandwidth) sub-section

for the tradeoffs.

DC gain accuracy is usually limited by the tolerance of

Rf and Rg.

DC Gain (transimpedance)

Figure 3 shows a transimpedance circuit where the

current Iin is injected at the inverting node. The current

source’s output resistance is much greater than Rf.

The DC transimpedance gain is:

The recommended Rf is 3kΩ. Parasitic capacitance at

the inverting node may require a slight increase of Rf to

maintain a flat frequency response.

DC gain accuracy is usually limited by the tolerance

of Rf.

CLC408

0.1

µF

6.8

µF

Vin

VCC

0.1

µF

6.8

µF

VEE

−

=−

CLC408

0.1

µF

6.8

µF

Vin

VCC

0.1

µF

6.8

µF

VEE

== −

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