T0506ST datasheet(4/8 Pages) CITC

4 / 8 page

Application Information

Pin Connection in PCB

lines simultaneously. The pin connection is shown

in the ﬁgure below.

Four parallel data lines, from inner IC to I/O port

connector,

coule connect to T0506ST six I/O pins

directly. Pin 9 of T0506ST is the GND pin, which

should connect to the

GND of PCB. The wire should

be as short as possible in order to minimize the

parasitic inductance.

PCB Layout Guidelines

For optimum ESD protection and the whole circuit

performance, the following PCB layout guidelines are

recommended:

should be as short as possible. It could

reduce the

ESD transient return path to GND.

The vias connecting T0506ST GND pins to the

PCB GND should be wide

Place

possible. It could reduce the parasitic inductance

and restrict ESD coupling into adjacent traces.

Avoid running critical signals near board edges.

T0506ST GND pin to the PCB GND rail path

T0506ST as close to the connector port as

T0506ST provides ESD protection for six data

I/O1

I/O2

GND

VCC ﬂoated

To Connector

I/O4

I/O5

To Inner IC

I/O3

I/O6

To Inner IC

To Connector

Figure 2 T0506ST pin connection in PCB providing data line protection.

VCC pin is left as ﬂoating when no VCC rail is presented in PCB.

I/O1

I/O2

GND

VCC

To Connector

I/O4

I/O5

To Inner IC

I/O3

I/O6

To Inner IC

To Connector

0.1 F

Figure 1

pin connection in PCB providing data lines

and power rail line protection.

T0506ST

Chip Integration Technology Corporation

Document ID : DS-22V11

Revised Date : 2016/08/30

Revision : C

Ultra-Low Capacitance ESD Protection Device

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