AD6652BBC datasheet(34/76 Pages) AD

34 / 76 page

AD6652

Rev. 0 | Page 34 of 76

umulator is cleared

et is

e beginning phase for the new

frequ ncy.

Reserved Bits

put

en Input Port B is

connected to the selected filter channel. If this bit is cleared,

then Input Port A is connected to the

lected filter channel.

Sync Pin Select

Bits 7 and 8 of the NCO control register determine which

ync pins: SYNCA, SYNCB, SYNCC, and

be enabled in

nal

ecifi

in.

ble

ss R

ts to

se a

dre

Bit 0x88:7

ted

c Pin

Clear Phase Accumulator on Hop

When Bit 3 is logic high, the NCO phase acc

(set to all zeros) at the beginning of the next frequency change.

This ensures a consistent phase of the NCO on each hop by

defeating the phase continuous feature. The NCO phase offs

unaffected by this setting. If phase continuous hopping is

desired, this bit should be cleared so that the last phase in the

NCO phase register becomes th

Bits 4 and 5 are reserved and should be written to Logic 0.

Input Select

Bit 6 of the NCO control register at Address 0x88 controls in

port selection. If this bit is set high, th

external sync pin (if any) is assigned to the channel of interes

The AD6652 has four s

SYNCD. Any sync pin can be assigned to any or all four receiver

channels of the AD6652; however, a channel can have only one

sync pin assigned to it. The sync pin(s) must als

the PIN_SYNC control register at Address 4 of the exter

mem ry map. T ble 13 s ows the it values sed to s ect a

c extern sync p

13. Prog ammin Chann Addre

egister (CAR)

Choo

Sync Pi for a

lected

ss/Bit 0

8:8

dress/

Selec

Syn

SYNC

SYNCD

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