AD9608

Data Sheet

Rev. C | Page 6 of 40

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless

otherwise noted.

Table 3.

Parameter

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

0.9

V

Differential Input Voltage

Full

0.3

3.6

V p-p

Input Voltage Range

Full

AGND − 0.3

AVDD + 0.2

V

Input Common-Mode Range

Full

0.9

1.4

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

−10

+10

µA

Input Capacitance

Full

4

pF

Input Resistance

Full

8

10

12

kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage

Full

1.22

DRVDD + 0.2

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

40

132

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUT (SCLK/DFS/SYNC)2

High Level Input Voltage

Full

1.22

DRVDD + 0.2

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current (VIN = 1.8 V)

Full

−92

−135

µA

Low Level Input Current

Full

−10

+10

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUT/OUTPUT (SDIO/DCS)1

High Level Input Voltage

Full

1.22

DRVDD + 0.2

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

−10

+10

µA

Low Level Input Current

Full

38

128

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

5

pF

LOGIC INPUTS (OEB, PDWN)2

High Level Input Voltage

Full

1.22

DRVDD + 0.2

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current (VIN = 1.8 V)

Full

−90

−134

µA

Low Level Input Current

Full

−10

+10

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

5

pF

DIGITAL OUTPUTS

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage

Full

1.79

V

Full

1.75

V

Low Level Output Voltage

Full

0.2

V

Full

0.05

V