AD9250 datasheet(2/45 Pages) AD

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AD9250

Data Sheet

Rev. E | Page 2 of 45

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

Specifications..................................................................................... 5

ADC DC Specifications............................................................... 5

ADC AC Specifications ............................................................... 6

Digital Specifications ................................................................... 7

Switching Specifications .............................................................. 9

Timing Specifications ................................................................ 10

Absolute Maximum Ratings.......................................................... 11

Thermal Characteristics ............................................................ 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Typical Performance Characteristics ........................................... 14

Equivalent Circuits......................................................................... 18

Theory of Operation ...................................................................... 20

ADC Architecture ...................................................................... 20

Analog Input Considerations.................................................... 20

Voltage Reference ....................................................................... 21

Clock Input Considerations...................................................... 21

Power Dissipation and Standby Mode..................................... 24

Digital Outputs ............................................................................... 25

JESD204B Transmit Top Level Description............................ 25

JESD204B Overview .................................................................. 25

JESD204B Synchronization Details ......................................... 26

Link Setup Parameters............................................................... 26

Frame and Lane Alignment Monitoring and Correction..... 30

Digital Outputs and Timing ..................................................... 30

ADC Overrange and Gain Control.......................................... 32

ADC Overrange (OR)................................................................ 32

Gain Switching............................................................................ 32

DC Correction ................................................................................ 33

DC Correction Bandwidth........................................................ 33

DC Correction Readback.......................................................... 33

DC Correction Freeze................................................................ 33

DC Correction (DCC) Enable Bits .......................................... 33

Serial Port Interface (SPI).............................................................. 34

Configuration Using the SPI..................................................... 34

Hardware Interface..................................................................... 34

SPI Accessible Features.............................................................. 35

Memory Map .................................................................................. 36

Reading the Memory Map Register Table............................... 36

Memory Map Register Table..................................................... 37

Memory Map Register Description ......................................... 41

Applications Information .............................................................. 42

Design Guidelines ...................................................................... 42

SPI Initialization Sequence ....................................................... 42

Outline Dimensions....................................................................... 45

Ordering Guide .......................................................................... 45

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